Eurotech ED-C3 02 Spezifikationen PDF herunterladen (Seite 17)

Hardware Specifications

DPD5MAN101

3.4. I/O

CPU-71-15 has the following interfaces to external devices.

3.4.1. GPIO

CPU-71-15 has a GPI control register and a GPO control register. The features of GPIO are shown

below.

3.4.1.1. GPI

CPU-71-15 is equipped with 4 general inputs. They can be read out from the Intel QM67 PCH register.

GPI is set as input pin in BIOS. The register where GPI is allocated is shown in Table 13. If the GPI

line’s jumper is closed, that GPI line will be connected to its corresponding GPO line. For example, if

JP5 is shunted (closed), the GPO2 will be routed to GPI2.

Table 13. GPI control register

Signal

Intel QM67connecting pin Supporting register Bit

Jumper

GPI0

GPIO68 GP_LVL3 bit 4

JP3

GPI1

GPIO69 GP_LVL3 bit 5

JP4

GPI2

GPIO70 GP_LVL3 bit 6

JP5

GPI3

GPIO71 GP_LVL3 bit 7

JP6

High logic level (“1”) is read from the register while High level voltage is applied to the input pin, and

Low logic level (“0”) is read from the register while Low level voltage is applied to the input pin. Please

refer to 7.2. Electrical Specifications on page 28 for electrical specifications.

3.4.1.2. GPO

CPU-71-15 is equipped with 4 general outputs. Status can be changed by writing in the Intel QM67

PCH register. GPO is set as the output pin in BIOS. The register where GPO is allocated is shown in

Table 14.

Table 14. GPO control register

Signal

Intel QM67connecting

Supporting register Bit

Initial setting

(logic level)

GPO0

GPIO8 GP_LVL bit 8 High

GPO1

GPIO15 GP_LVL bit 15 Low

GPO2

GPIO24 GP_LVL bit 24 Low

GPO3

GPIO28 GP_LVL bit 28 Low

It outputs High level voltage when High logic level (“1”) is written in the register, while it outputs Low

level voltage when Low logic level (“0”) is written in it. Please refer to 7.2. Electrical Specifications on

page 28 for electrical specifications.

3.4.2. Graphics LVDS

CPU-71-15 has an LVDS port, available at front panel connector J27.

It is confirmed to operate at the resolution of 1920×1200.

3.4.3. Analog VGA

CPU-71-15 has an Analog VGA port, available at front panel connector J26.

3.4.4. Suspend Status

CPU-71-15 routes the SUS_STAT#/SUS_S3#/SUS_S4#/SUS_S5# signals to LEDs. See Section 6.2

for LED locations and descriptions.

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