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First edition – J DIGITAL TECwww.euJune 2013 – DPCHNOLOGIESrotech.coPD5MAN101 S FOR A BETTom TER WORLD CPPU-71-Core i7US-15 (D7 VMEbus SSER MANDPD5)

CPU-71-15 - User Manual 10 DPD5MAN101 2.2. Block Diagram CPU-71-15 Block Diagram is shown in Fig.1. Fig.1 Block Diagram

Hardware Specifications 11DPD5MAN101 3. Hardware Specifications 3.1. Processor 3.1.1. Processor Options  Intel’s ®CoreTM i7-2610UE Mobile Dual Core

CPU-71-15 - User Manual 12 DPD5MAN101 3.1.4. Memory Address Map Memory space Address Map is shown in Table 2. Table 2. Memory space Address Map D

Hardware Specifications 13DPD5MAN101 3.1.5.2. Status Register (offset：0001h) This register shows the logic of SPD Write Protect signal and input sig

CPU-71-15 - User Manual 14 DPD5MAN101 3.2.3. External Memory Interface CPU-71-15 has the following 2 external memory interfaces for mass storage devi

Hardware Specifications 15DPD5MAN101 3.3.2. PCI Express CPU-71-15 is compliant with PCI Express Rev2.0 standard. The CPU has 16 lanes of PCI Expres

CPU-71-15 - User Manual 16 DPD5MAN101 3.3.7. PCI CPU-71-15 has a 32bit/33MHz PCI bus compliant with the PCI Local Bus Specification Revision 2.3 stan

Hardware Specifications 17DPD5MAN101 3.4. I/O CPU-71-15 has the following interfaces to external devices. 3.4.1. GPIO CPU-71-15 has a GPI control re

CPU-71-15 - User Manual 18 DPD5MAN101

Mechanical Specifications 19DPD5MAN101 4. Mechanical Specifications CPU-71-15 is compliant with the VMEbus & VME64 Specification. Mechanical spe

© 2013 Dynatem Inc. Preface Thank you for choosing the CPU-71-15. Please read this manual before using the CPU-71-15 so that you may obtain the gre

CPU-71-15 20 4.2. FroThe D11408 - User Manont PanDPD5’s fron84RS.375CSual nel t panel usesSS12). The iFig. s a non-staniridite finish i3. Front pan

Mechanical Specifications 21DPD5MAN101 4.3. Heat Sink The CPU-71-15 comes with a heat sink. The heat sink mainly comes in contact with the CPU, the

CPU-71-15 - User Manual 22 DPD5MAN101

DPD5MAN15. PM5.1. Op5.1.1. GenV T5.1.2. VI/OT5.1.3. JN4Tbco5.1.4. MecTca 101 MC Supptional Pneral Versions of ththey confa x8 XMCUSB portUSB port

CPU-71-15 - User Manual 24 DPD5MAN101 5.2. Power Sequence  12V and 5VDC on the VMEbus have no power sequence but 12 VDC is required to switch on th

Connectors and Jumpers 25DPD5MAN101 6. Connectors, Jumpers, and LEDs 6.1. CPU-71-15 Placement Plans A photograph of the CPU-71-15, component side, i

CPU-71-15 - User Manual 26 DPD5MAN101 6.2. On-board Jumpers and LEDs Fig.6 Locations of User Option Jumpers & LEDs 6.2.1. User and Factory Opti

Connectors and Jumpers 27DPD5MAN101 6.2.2. On-board LEDs The CPU-71-15 has LEDs that provide info on system status and are shown in figure 6, above.

CPU-71-15 - User Manual 28 DPD5MAN101 6.3.5. J2 Dual Front Panel SATA Port Connector Connector J2 provides two SATA ports accessible at the front pan

Connectors and Jumpers 29DPD5MAN101 6.3.7. J27 Front Panel LVDS Connector J27 is a Single-in-line Molex connector accessible from the front panel th

Table of Contents 3DPD5MAN101 Table of Contents Document Revision History ...

CPU-71-15 - User Manual 30 DPD5MAN101 6.3.10. P1 & P2 & P0 (VMEbus backplane connectors) P1, P2 are the VMEbus connectors populated on standa

Connectors and Jumpers 31DPD5MAN101 Table 18. P2 VMEbus connector Row A Row B Row C Row D Row ZPin Signal Pin Signal Pin Signal Pin S

CPU-71-15 - User Manual 32 DPD5MAN101

System Specifications 33DPD5MAN101 7. System Specifications 7.1. Power Supply Power to the CPU-71-15 is supplied through P1 & P2 (VMEbus backpla

CPU-71-15 - User Manual 34 DPD5MAN101

BIOS Setup 35DPD5MAN101 8. BIOS Setup The CPU-71-15 is equipped with the Phoenix Technologies Ltd. SecureCore Tiano BIOS, customized for this partic

CPU-71-15 - User Manual 36 DPD5MAN101 8.1.4. Boot Features Table 3. Boot Features Menu Setting Setting Contents NumLock Set NumLock status at sta

BIOS Setup 37DPD5MAN101 8.2. Advanced Menu 8.2.1. Select Language Table 4. Select Language Setting Setting Contents Select Language Language ca

CPU-71-15 - User Manual 38 DPD5MAN101 8.2.3. Processor Configuration 8.2.3.1. Processor Power Management Table 6. Processor Configuration Setting

BIOS Setup 39DPD5MAN101 8.2.3.2. Processor Power Management Table 7. Processor Power Management Setting Setting Contents Intel Speed Step (R)

CPU-71-15 - User Manual 4 DPD5MAN1015.1.4. Mechanical Drawing ...

CPU-71-15 - User Manual 40 DPD5MAN101 Setting Contents Lock TDP setting Lock of TDP MSR_CONFIG_TDP_CONTROL. ・Disabled(Default) - disable ・Enabled -

BIOS Setup 41DPD5MAN101 8.2.4. Peripheral Configuration Table 8. Peripheral Configuration Setting Setting Contents Spread Spectrum Clock Enable

CPU-71-15 - User Manual 42 DPD5MAN101 8.2.6. Memory Configuration Table 10. Memory Configuration Setting Setting Contents Memory Frequency Limit

BIOS Setup 43DPD5MAN101 8.2.7. System Agent (SA) Configuration 8.2.7.1. DMI Settings Table 11. DMI Setting Setting Contents DMI Link ASPM Contro

CPU-71-15 - User Manual 44 DPD5MAN101 Setting Contents DVMT Total Gfx Mem Set DVMT5.0 DVMT graphic memory size. Invalid when external graphics is

BIOS Setup 45DPD5MAN101 Setting Contents GMCH BLC Control Select GMCH BLC control. ・PWM - Inverted (Default) ・GMBUS - Inverted ・PWM - Normal ・GMB

CPU-71-15 - User Manual 46 DPD5MAN101 8.2.7.4. PEG Port Configuration Table 14. PEG Port Configuration Setting Setting Contents PEG 0 – Gen X Se

BIOS Setup 47DPD5MAN101 8.2.8. South Bridge Configuration Table 15. South Bridge Configuration Setting Setting Contents HPET Support Set HPET (

CPU-71-15 - User Manual 48 DPD5MAN101 Setting Contents Gen3 Equalization Implementation of PEG Gen3 equalization procedure. ・Disabled ・Enabled (Defa

BIOS Setup 49DPD5MAN101 8.2.8.3. PCI Express Port 3～5 Configuration Table 18. PCI Express Port 3～5 Configuration Setting Setting Contents PCI Exp

Important User Information 5DPD5MAN101 1. Important User Information In order to lower the risk of personal injury, electric shock, fire, or equipmen

CPU-71-15 - User Manual 50 DPD5MAN101 8.2.9. Network Configuration Table 21. Network Configuration Setting Setting Contents PCH Internal LAN Set

BIOS Setup 51DPD5MAN101 8.2.11. SMBIOS Event Log Table 44. SMBIOS Event Log Setting Setting Contents Event Log Enable/disable of event log. ・Di

CPU-71-15 - User Manual 52 DPD5MAN101 8.2.13. Thermal Configuration Table 46. Thermal Configuration Setting Setting Contents Platform Thermal Co

BIOS Setup 53DPD5MAN101 Setting Contents PCH Temp Read Enable *19 Set PCH temperature read. ・Disabled ・Enabled (Default) PCH Temp Read Enable *19

CPU-71-15 - User Manual 54 DPD5MAN101 8.2.15. Intel Rapid Start Technology Table 48. Intel Rapid Start Technology Setting Setting Contents iRST S

BIOS Setup 55DPD5MAN101 8.5. Exit Menu Table 51. Exit Menu Setting Setting Contents Exit Saving Changes Exits the setup menu with saving all the

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CPU-71-15 - User Manual 6 DPD5MAN101 Protect the product from water and chemicals Contact between the product and water or chemicals can result in pr

Important User Information 7DPD5MAN101 Use antistatic precautions This product comprises electronic parts that are highly susceptible to static elect

CPU-71-15 - User Manual 8 DPD5MAN101

Summary 9DPD5MAN101 2. Summary CPU-71-15 is a VMEbus Single Board Computer (SBC) Module based on Intel® CoreTM i7 mobile processor. It is compatibl