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Am186™CC Microcontroller Router Reference Design User’s Manual

D-4

END divider;

STATE_MACHINE DPLL CLOCKED_BY mclk_c32 RESET_BY resout;

" Jitter reduction circuit, implemented as free running up-counter,

" that counts 15, 16 or 17 clock cycles to form a window.

" The entire circuit can be viewed as a DPLL

STATE one:

pclk=1; " set the PCLK output to one

goto two; " on the next rising edge of the CLK signal go to the next state !

STATE two:

pclk=1;

goto three;

STATE three:

pclk=1;

goto four;

STATE four:

pclk=1;

goto five;

STATE five:

pclk=1;

goto six;

STATE six:

pclk=1;

goto seven;

STATE seven:

pclk=1;

goto eight;

STATE eight:

pclk=0;

goto nine;

STATE nine:

pclk=0;

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Eurotech BRI ISDN Bedienungsanleitung Seite 80